HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 345

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
26
25
24
23, 22
21
20
Bit
Name
DPUP
⎯
OPUP
⎯
A1MBC
A4MBC
Initial
Value
0
0
0
All 0
0
0
R/W
R/W
R
R/W
R
R/W
R/W
Description
Data Pin Pull-Up Resistor Control
Specifies the pull-up resistor status of the data pins (D31
to D0). It is initialized by a power-on reset. The pins are
not pulled up when access is performed or when the bus
is released, even if the pull-up resistor is on.
0: Cycle is provided for turning on the pull-up resistor for
1: Pull-up resistor is off for data pins (D31 to D0).
Note: *It is recommended that a pull-up resistor be
Reserved
This bit is always read as 0. The write value should
always be 0.
Control Output Pin Pull-Up Resistor Control
Specifies the pull-up resistor status (A[25:0], BS, CSn,
RD, WEn, RD/WR, RAS, CE2A, CE2B) when the control
output pins are high-impedance. This bit is initialized by a
power-on reset.
0: Pull-up resistor is on for control output pins (A[25:0],
1: Pull-up resistor is off for control output pins (A[25:0],
Reserved
These bits are always read as 0. The write value should
always be 0.
Area 1 SRAM Byte Control Mode
MPX interface has priority when MPX interface is set.
This bit is initialized by a power-on reset.
0: Area 1 SRAM is set to normal mode
1: Area 1 SRAM is set to byte control mode
Area 4 SRAM Byte Control Mode
MPX interface has priority when MPX interface is set.
This bit is initialized by a power-on reset.
0: Area 4 SRAM is set to normal mode
1: Area 4 SRAM is set to byte control mode
data pins (D31 to D0) before and after memory
access.*
BS, CSn, RD, WEn, RD/WR, RAS, CE2A, CE2B)
BS, CSn, RD, WEn, RD/WR, RAS, CE2A, CE2B)
externally attached for the data pins if it is
required.
Rev. 2.00 Feb. 12, 2010 Page 261 of 1330
REJ09B0554-0200