HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 147

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

point load or store requires execution of two 32-bit data size operations with the SZ bit in FPSCR
cleared to 0.
3.7
3.7.1
When using the Round to Nearest rounding mode, the underflow flag may not be set in cases
defined as underflow by the IEEE754 standard.
Under the IEEE754 standard, when the Round to Nearest rounding mode is used and infinite-
precision operation result x is (i) or (ii) (single-precision) or (iii) or (iv) (double-precision), there
are cases where “the result after rounding is a normalized number, but an underflow results.”
In such cases where “the result after rounding is a normalized number, but an underflow results,”
the FPU does not set the underflow flag to 1. In these cases the operation result, the value written
to FRn, is correct. Also, if an FPU exception occurs, the underflow flag is not set to 1 but the
inexact flag is set to 1 in such cases. Generation of FPU exceptions can be enabled by setting the
enable field to 1.
(i) H'007FFFFF < x < H'00800000
(ii) H'807FFFFF > x > H'80800000
(iii) H'000FFFFF FFFFFFFF < x < H'00100000 00000000
(iv) H'800FFFFF FFFFFFFF > x > H'80100000 00000000
Examples
• Single-precision
• Double-precision
When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 0 (single-precision), and the
FMUL instruction (H'00FFF000 * H'3F000800) is executed.
a. According to IEEE754 standard
b. FPU
When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 1 (double-precision), and the
FDIV instruction (H'001FFFFF FFFFFFFF / H'40000000 00000000) is executed.
a. According to IEEE754 standard
Operation result: H'00800000
FPSCR: H'0004300C
Operation result: H'00800000
FPSCR: H'00041004
Usage Notes
Rounding Mode and Underflow Flag
Rev. 2.00 Feb. 12, 2010 Page 63 of 1330
REJ09B0554-0200