HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 725

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
1
Bit
Name
WAIT_ER
Initial
Value
0
R/W
R/W
Description
Wait Error
Indicates the wait timer error status.
0: Indicates that the interval between the start of two
[Clearing Conditions]
•
•
1: Indicates that the interval between the start of two
[Setting Conditions]
•
•
Notes: 1. Even if the RE bit in SISCR is cleared to 0, the
successive characters has not exceeded the etu set by
SIWAIT.
successive characters has exceeded the etu set by
SIWAIT.
On reset
When 0 is written to WAIT_ER while its value is 1
In T = 0 mode, when the interval between the start of two
successive characters exceeds the etu (value of 60 x
SIWAIT: working wait time).
In T = 1 mode, when the interval between the start of two
successive characters exceeds the etu (SIWAIT value:
Guardtime).
2. In T = 0 mode, changing the RE bit from 0 to 1
3. In T = 0 mode, to avoid making the WAIT_ER bit
WAIT_ER flag is unaffected, and the previous
state is maintained.
may not set the WAIT_ER bit, even if the setting
conditions for the WAIT_ER bit are satisfied. In
this condition, the WAIT_ER bit is set at the timing
of 60 × (SCWAIT + n) etu after the last
transmission or reception. n is a whole number
and it depends on the timing at which the RE bit is
set.
set at the timing of 60 × (SCWAIT + n) etu after
the last transmission or reception, the following
procedure should be followed: Change the
protocol bit (PB) in the smart card mode register
(SISCMR) from 0 to 1 and again change the PB
bit to 0.
In T = 1 mode, to avoid making the WAIT_ER bit
set at the timing of (SCWAIT) etu after the last
reception, the following procedure should be
followed:
Change the PB bit in SISCMR from 1 to 0 and
again change the PB bit to 1.
Rev. 2.00 Feb. 12, 2010 Page 641 of 1330
REJ09B0554-0200