HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 196

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.4
The following are additional notes on pipeline operation and the method of calculating the number
of clock cycles.
The number of states (CPU clock cycles) required for stages where an external bus access, etc.,
occurs may include an increased number of cycles, in addition to the number of memory access
cycles set by the bus state controller (BSC), etc.
For example, the occurrence of the following may result in idle cycles as observed from the
external bus.
1. Transfer of data from the logical address bus to the physical address bus
2. Transfer of data between buses using different operation clocks
The stages where external memory access occurs include some instruction fetch (I) and some
memory access (MA) stages.
Rev. 2.00 Feb. 12, 2010 Page 112 of 1330
REJ09B0554-0200
5. In the case of consecutive executions of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/
6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn
7. When an LDS to MACH/MACL is followed by MAC.W/MAC.L/MUL.L/MULS.W/
8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that
9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction,
Usage Note
DMULS.L/DMULU.L, latency is decreased to 2 cycles.
instruction, latency of the LDS to MACH/MACL is 4 cycles.
MULU.W/DMULS.L/DMULU.L, latency of the LDS to MACH/MACL is 1 cycle.
reads from or writes to a floating-point register, the aforementioned LS group
instructions cannot be executed in parallel.
latency of the single-precision FTRC instruction is 1 cycle.