HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 202

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 7.6.4, OC Data Array.
The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address
array. For details, see section 6.6.4, UTLB Address Array.
The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1
and 2. For details, see section 6.6.5, UTLB Data Array 1, and section 6.6.6, UTLB Data Array 2.
The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area.
(2) External Memory Space
The SH-4 supports a 29-bit external memory space. The external memory space is divided into
eight areas as shown in figure 6.4. Areas 0 to 6 relate to memory, such as SRAM, synchronous
DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 10, Bus State Controller
(BSC).
(3) Virtual Address Space
Setting the AT bit in MMUCR to 1 enables the P0, P3, and U0 areas of the physical address space
in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte page
units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be
increased to a maximum of 256. This is called the virtual address space. Mapping from the virtual
address space to the 29-bit external memory space is carried out using the TLB. Only when area 7
in the external memory space is accessed using the virtual address space, addresses H'1C00 0000
to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area
control register area in the physical address space. The virtual address space is shown in figure
6.5.
Rev. 2.00 Feb. 12, 2010 Page 118 of 1330
REJ09B0554-0200
Figure 6.4 External Memory Space
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Area 7 (reserved area)
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6