HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 24

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
21.5.1 Storage Format
of Transfer Data
22.5.4 Interrupt
Request Register
(CANIRR)
22.5.5 Interrupt Mask
Register (CANIMR)
Rev. 2.00 Feb. 12, 2010 Page xxii of lxxxii
REJ09B0554-0200
Page
783
818
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Revision (See Manual for Details)
Description amended
The data in memory mentioned above and the data read by
the USB host must always correspond. When reading data
from external memory, the USB host always reads data in
longword units regardless of the endian setting. The USB
host assumes that read data is in the little endian order, that
is, the byte order that places the first byte in the lowest
address and the last byte in the highest address. That is,
during operation of this IC, data must be stored sequentially
in longword units in little endian order from low to high
addresses, regardless of whether the endian setting is little
endian or big endian.
An example of failure is shown in figure 21.4.
In this example, USB host controller does not receive #H'12,
which is the expected transfer data.
The USB host controller, when writing, stores data
sequentially starting with the low order bits in memory in little
endian order, so that the data is read/written correctly from
both sides regardless of the endian setting. That is, the data
is always aligned in little endian format.
Table amended
Table amended
Table amended
Bit
15
Bit
11, 10
Bit
15, 11,
10
⎯
⎯
⎯
Bit Name
Bit Name
Bit Name
Initial Value
0
Initial Value
All 0
Initial Value
All 1
R/W
R
R/W
R
R/W
R
Reserved
The write value should always be 0. The read
value is not guaranteed.
Reserved
The write value should always be 0. The read
value is not guaranteed.
Reserved
The write value should always be 1. The read
value is not guaranteed.
Description
Description
Description