HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 264

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• When MMU is off (AT = 0 in MMUCR)
7.7.4
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows according to whether the MMU is on or off. If an exception
occurs during a write to an SQ, the SQ contents before the write are retained. If an exception
occurs in a data transfer from an SQ to external memory, the transfer to external memory will be
aborted.
• When MMU is on (AT = 1 in MMUCR)
Rev. 2.00 Feb. 12, 2010 Page 180 of 1330
REJ09B0554-0200
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF
instruction is issued. The meanings of address bits [31:0] are as follows:
[31:26]
[25:6]
[5]
[4:2]
[1:0]
External address bits [28:26], which cannot be generated from the above address, are generated
from QACR0 and QACR1.
QACR0[4:2]
QACR1[4:2]
External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary.
Data transfer to a PCMCIA interface area in this LSI is always performed using the values of
the SA and TC bits in PTEA.
Operation is in accordance with the address translation information recorded in the UTLB, and
the SQMD bit in MMUCR. Write type exception judgment is performed for writes to the SQs,
and read type exception judgment for transfer from the SQs to external memory (using a PREF
instruction). As a result, a TLB miss exception, protection violation exception, or initial page
write exception is generated as required. However, if SQ access is enabled in privileged mode
only by the SQMD bit in MMUCR, an address error will occur even if address translation is
successful in user mode.
Determination of SQ Access Exception
: 111000
: Address
: 0/1
: Don't care
: 00
: External address bits [28:26] corresponding to SQ0
: External address bits [28:26] corresponding to SQ1
Store queue specification
External address bits [25:6]
0: SQ0 specification
1: SQ1 specification and external address bit [5]
No meaning in a prefetch
Fixed at 0