HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 200

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Access to a PCMCIA interface area by the CPU in SH7760 is always performed using the values
of the SA and TC bits in PTEA.
Access to a PCMCIA interface area by the DMAC is always performed using the SSAn, DSAn,
STC, and DTC values in CHCRn of the DMAC. For details, see section 11, Direct Memory
Access Controller (DMAC).
P0, P1, P3, and U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache.
Whether or not the cache is used is determined by the CCR setting. When the cache is used,
switching between the copy-back method and the write-through method for write accesses is
specified by the WT bit in CCR, except for in the P1 area. Switching in the P1 area is determined
by the CB bit in CCR. Replacing the upper 3 bits of an address in these areas with 0s gives the
corresponding external memory space address. However, since area 7 in the external memory
space is a reserved area, a reserved area will exist in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, clearing the upper 3 bits
of an address to 0 gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area will exist in this area.
P4 Area: The P4 area is mapped onto SH-4 on-chip I/O memory. The P4 area cannot be accessed
using the cache. The P4 area is shown in detail in figure 6.3.
Rev. 2.00 Feb. 12, 2010 Page 116 of 1330
REJ09B0554-0200
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
Figure 6.2 Physical Address Space (AT = 0 in MMUCR)
Privileged mode
Non-cacheable
Non-cacheable
Cacheable
Cacheable
Cacheable
P0 area
P1 area
P2 area
P3 area
P4 area
memory space
External
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Store queue area
Address error
Address error
User mode
Cacheable
U0 area
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF