HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 29

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
Section 28 User
Debug Interface (H-
UDI)
Figure 28.1 H-UDI
Block Diagram
28.1 Input/Output Pins
Table 28.1 Pin
Configuration
29.1 Features
29.3.2 A/D
Control/Status Register
(ADCSR)
Page
1020
1022
1039
1045
1046
Revision (See Manual for Details)
Figure amended
Figure amended
Description amended
•
Table amended
Pin Name
Emulator
CAN0_NERR/AUDSYNC
Bit
13
Bit
11
10
CAN0_RX/AUDATA[2]
CAN1_RX/AUDATA[3]
CAN0_TX/AUDATA[0]
CAN1_TX/AUDATA[1]
CAN1_NERR/AUDCK
Reserved/AUDATA[1]
Reserved/AUDATA[2]
Reserved/AUDATA[3]
Reserved/AUDSYNC
A/D conversion can be externally triggered (except in multi
mode)
ADTRG/AUDATA[0]
Bit
Name
ADST
Bit
Name
TRGE1
TRGE0
Reserved/AUDCK
AUDSYNC/
Abbreviation
AUDCK/
AUDATA[3] to
AUDATA[0]
Initial
Value
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
R/W
I/O
Output Emulator Connection
Rev. 2.00 Feb. 12, 2010 Page xxvii of lxxxii
Description
A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion. It can also be set to 1 by external
trigger input (ADTRG) pin (except in multi mode).
0: A/D conversion is stopped
1:
Description
Trigger Enable
External trigger input permits or prohibits A/D conversion.
These bits must be set while conversion is stopped.
00: When an external trigger is input, A/D conversion
01: Setting prohibited
10: Setting prohibited
11: A/D conversion starts at the falling edge of an input
Note: Clear bits TRGE1 and TRGE0 to 0 before
Function
When bit 13 of IPSELR in the PFC is set to 1,
signals are output to the following pins.
CAN0_TX/AUDATA[0]
CAN1_TX/AUDATA[1]
CAN0_RX/AUDATA[2]
CAN1_RX/AUDATA[3]
CAN0_NERR/AUDCK
CAN1_NERR/AUDSYNC
When bit 12 of IPSELR in the PFC is set to 1,
signals are output to the following pins.
ADTRG/AUDATA[0]
Reserved/AUDATA[1]
Reserved/AUDATA[2]
Reserved/AUDATA[3]
Reserved/AUDCK
Reserved/AUDSYNC
does not start
signal from the external trigger input pin (ADTRG)
(except in multi mode)
switching the trigger signal.
Trace controller
IPSELR
REJ09B0554-0200
When Not
in Use
Open*
PFC
4