HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 918

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• CANRFPR0
Initial value:
Note: * Only a write of 1 is allowed to clear the bit.
22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0)
The CANMBIMR are two 16-bit read/write registers. The CANMBIMR only prevents the setting
of IRR related to the Mailbox activities (IRR1: Data Frame Received Interrupt, IRR2: Remote
Frame Request Interrupt, IRR8: Mailbox Empty Interrupt, and IRR9: Message Overrun Interrupt).
If a Mailbox is configured as receive, a mask at the corresponding bit position prevents the
generation of receive interrupts (IRR1 and IRR2 and IRR9) but does not prevents the settings of
the corresponding bit in CANRXPR or CANRFPR or CANUMSR. Similarly, when a mailbox has
been configured for transmission, a mask prevents the generation of in Interrupt signal and setting
of an Mailbox Empty Interrupt due to successful transmission or transmission abortion (IRR8),
however, it does not prevent the HCAN2 from clearing the corresponding CANTXPR/CANTXCR
bit and setting the CANTXACK bit for abortion of transmission.
A mask is set by writing a 1 to the corresponding bit for the Mailbox activity to be masked. At
reset, all Mailbox interrupts are masked.
• CANMBIMR1
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 834 of 1330
REJ09B0554-0200
15 to 0
Bit
R/W:
R/W:
Bit:
Bit:
RFPR0[15:0]
RFPR0
MBIMR1
R/W*
R/W
_15
_15
15
15
0
1
Bit Name
RFPR0
MBIMR1
R/W*
R/W
_14
_14
14
14
0
1
RFPR0
MBIMR1
R/W*
R/W
_13
13
13
_13
0
1
RFPR0
MBIMR1
R/W*
All 0
R/W
_12
12
Initial Value
12
_12
0
1
MBIMR1
RFPR0
R/W*
R/W
_11
_11
11
11
0
1
MBIMR1
RFPR0
R/W*
R/W
_10
_10
10
10
0
1
R/W*
MBIMR1
RFPR0
R/W*
R/W
R/W
_9
_9
9
0
9
1
RFPR0
MBIMR1
R/W*
R/W
_8
_8
8
0
8
1
Remote request pending flags for Mailboxes
15 to 0 respectively.
0: Clearing condition: Write a 1 to this bit.
1: Corresponding Mailbox received Remote
RFPR0
MBIMR1
R/W*
Frame
Setting condition: Completion of remote
frame reception in the corresponding
Mailbox
R/W
_7
_7
7
0
7
1
RFPR0
MBIMR1
R/W*
R/W
_6
_6
0
1
6
6
RFPR0
MBIMR1
R/W*
R/W
_5
_5
5
0
5
1
Description
RFPR0
MBIMR1
R/W*
R/W
_4
_4
4
0
4
1
RFPR0
MBIMR1
R/W*
R/W
_3
_3
3
0
3
1
RFPR0
MBIMR1
R/W*
R/W
_2
_2
2
0
2
1
MBIMR1
RFPR0
R/W*
R/W
_1
_1
1
0
1
1
MBIMR1
RFPR0
R/W*
R/W
_0
_0
0
0
0
1