HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 785

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.6.3
In order to set up the master interface for transmitting data packets to the I
and reading data back from the slave, take the following steps.
(1) Load the clock control register:
(a) Set SCL clock generation divider (SCGD) 01h.
(b) Set clock division ratio (CDF) is set to 2h.
(2) Load the master control register and address:
(a) Set address of slave being accessed to the master address register and the STM1 bit (write
(b) Set the master control register to 89h.
(3) Wait for the address to be output:
(a) Wait for master device’s events (interrupts by the MAT bit and the MDE bit in the master
(b) Set address of slave being accessed to the master address register and the STM1 bit (read
(c) Reset the MAT bit to 0.
(4) Wait for the address to be output:
(a) Wait for master device’s events (interrupts by the MAT bit and the MDR bit of the master
(b) Set the master control register to 88h.
(c) Reset the MAT bit to 0.
(b) Wait for a master device's event (the MST bit in the master status register).
(c) Reset the MST bit to 0.
(SCL frequency of 400 kHz)
(Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz)
mode: 0).
(MDBS = 1, MIE = 1, and ESG = 1)
status register).
mode: 1).
If the enable start generation bit in the master control register is still set to 1, the master will
issue a restart at the end of the byte transmission. Since the new address has been loaded as
described above, the bus direction will be turned around.
status register).
(The master device holds the SCL low level in order to suspend the data reception until the
MDR bit is cleared to 0).
Master Transmitter—Restart—Master Receiver (Single Buffer Mode)
Rev. 2.00 Feb. 12, 2010 Page 701 of 1330
Section 19 I
2
C bus, issuing a restart,
REJ09B0554-0200
2
C Bus Interface