HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 467

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Pin Name
DREQ acceptance
confirmation
DMA transfer end
notification
Ch.
2
Notes: 1. Pin DRAK0 or DRAK1 indicates the start of execution only in external request 2-
11.3
The DMAC has the following registers. For details of register addresses and register states during
each process, see section 32, List of Registers. For details regarding the DMA pin control register
(DMAPCR), see section 24.2.34, DMA Pin Control Register (DMAPCR), in section 24, Pin
Function Controller (PFC). In later descriptions, channel numbers are not explicitly mentioned.
Table 11.2 Register Configuration (1)
0
1
Register Name
DMA source address register 2
DMA destination address register 2 DAR2
DMA transfer count register 2
DMA channel control register 2
DMA source address register 0
DMA destination address register 0 DAR0
DMA transfer count register 0
DMA channel control register 0
DMA source address register 1
DMA destination address register 1 DAR1
DMA transfer count register 1
DMA channel control register 1
2. Pins DRAK2 and DACK2 are multiplexed.
3. Pins DRAK3 and DACK3 are multiplexed.
Register Descriptions
channel mode.
DRAK3/
DACK3
Abbreviation I/O
DRAK3
DACK3
Abbrev.
SAR0
DMATCR0 R/W
CHCR0
SAR1
DMATCR1 R/W
CHCR1
SAR2
DMATCR2 R/W
CHCR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output
Output
P4 Address
H'FFA0 0020
H'FFA0 0024
H'FFA0 0028
H'FFA0 002C
H'FFA0 0000
H'FFA0 0004
H'FFA0 0008
H'FFA0 000C
H'FFA0 0010
H'FFA0 0014
H'FFA0 0018
H'FFA0 001C
Function
Notifies acceptance of DMA transfer
request to external device which has
output DREQ3*
Strobe output to external device which
has output DREQ3, regarding DMA
transfer request*
Rev. 2.00 Feb. 12, 2010 Page 383 of 1330
Area 7 Address
H'1FA0 0004
H'1FA0 0008
H'1FA0 000C
H'1FA0 0010
H'1FA0 0014
H'1FA0 0018
H'1FA0 001C
H'1FA0 0020
H'1FA0 0024
H'1FA0 0028
H'1FA0 002C
H'1FA0 0000
3
3
REJ09B0554-0200
Size
32
32
32
32
32
32
32
32
32
32
32
32
Sync
Clock
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck