HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 355

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.5
WCR1 is a 32-bit readable/writable register that specifies the number of idle state insertion cycles
for each area. With some types of memory, data bus drive does not go off immediately after the
off-chip read signal goes off. As a result, there is a possibility of a data bus collision when
consecutive memory accesses are performed on memory in different areas, or when a memory
write is performed immediately after a read. In this LSI, idle cycles corresponding to the number
of cycles set in WCR1 are automatically inserted if there is a possibility of this kind of data bus
collision.
Initial value:
Initial value:
Bit
31
30
29
28
4n + 3
R/W:
R/W:
Bit:
Bit:
Bit
Name
⎯
DMAIW2
DMAIW1
DMAIW0
—
Wait Control Register 1 (WCR1)
31
15
R
R
0
0
-
-
DMA
IW2
R/W
R/W
IW2
30
14
A3
1
1
DMA
R/W
R/W
IW1
IW1
29
13
A3
1
1
Initial
Value
0
1
1
1
All 0
DMA
IW0
R/W
R/W
IW0
28
12
A3
1
1
27
11
R
R
R/W
R
R/W
R/W
R/W
R
0
0
-
-
IW2
R/W
IW2
R/W
A6
A2
26
10
1
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
DMAIW-DACK Device Inter-Cycle Idle Setting
These bits specify the number of idle cycles between
bus cycles to be inserted when switching from a device
with DACK to another space, or from a read access to a
write access on the same device. The DMAIW bits are
valid only for DMA single address transfer; with DMA
dual address transfer, inter-area idle cycles specified by
the AnIW2 to AnIW0 bits are inserted.
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
R/W
IW1
IW1
A6
A2
25
1
9
1
IW0
IW0
R/W
R/W
A6
A2
24
1
8
1
23
R
R
0
7
0
-
-
Rev. 2.00 Feb. 12, 2010 Page 271 of 1330
R/W
R/W
IW2
IW2
A5
A1
22
1
6
1
R/W
R/W
IW1
IW1
21
A5
A1
1
5
1
IW0
R/W
IW0
R/W
A5
A1
20
1
4
1
19
R
R
0
3
0
-
-
REJ09B0554-0200
R/W
R/W
IW2
IW2
18
A4
A0
1
2
1
R/W
R/W
IW1
IW1
17
A4
A0
1
1
1
R/W
R/W
IW0
IW0
A4
A0
16
1
0
1