HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 54

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.4 AC 97 Frame Slot Structure............................................................................................. 926
25.5 Operation ......................................................................................................................... 927
Section 26 Multimedia Card Interface (MMCIF) ............................................ 935
26.1 Features............................................................................................................................ 935
26.2 Input/Output Pins ............................................................................................................. 936
26.3 Register Descriptions ....................................................................................................... 937
26.4 Operation ......................................................................................................................... 967
26.5 MMCIF Interrupt Sources................................................................................................ 990
26.6 Operations when Using DMA.......................................................................................... 991
26.7 Register Accesses with Little Endian Specification......................................................... 994
26.8 Usage Notes ..................................................................................................................... 994
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25.5.1 Receiver .............................................................................................................. 927
25.5.2 Transmitter.......................................................................................................... 928
25.5.3 DMA ................................................................................................................... 928
25.5.4 Interrupts............................................................................................................. 928
25.5.5 Initialization Sequence........................................................................................ 929
25.5.6 Power-Down Mode............................................................................................. 934
25.5.7 Notes ................................................................................................................... 934
25.5.8 Reference ............................................................................................................ 934
26.3.1 Mode Register (MODER)................................................................................... 940
26.3.2 Command Type Register (CMDTYR)................................................................ 941
26.3.3 Response Type Register (RSPTYR) ................................................................... 942
26.3.4 Transfer Byte Number Count Register (TBCR) ................................................. 945
26.3.5 Command Registers 0 to 5 (CMDR0 to CMDR5) .............................................. 946
26.3.6 Response Registers 0 to 16 (RSPR0 to RSPR16) ............................................... 947
26.3.7 Command Start Register (CMDSTRT)............................................................... 949
26.3.8 Operation Control Register (OPCR) ................................................................... 950
26.3.9 Command Timeout Control Register (CTOCR) ................................................. 952
26.3.10 Data Timeout Register (DTOUTR) .................................................................... 953
26.3.11 Card Status Register (CSTR) .............................................................................. 954
26.3.12 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2) ................................... 956
26.3.13 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ................................. 958
26.3.14 Transfer Clock Control Register (CLKON)........................................................ 963
26.3.15 Data Register (DR) ............................................................................................. 964
26.3.16 FIFO Pointer Clear Register (FIFOCLR) ........................................................... 965
26.3.17 DMA Control Register (DMACR) ..................................................................... 966
26.3.18 Receive Data Timing Select Register (RDTIMSEL) .......................................... 967
26.4.1 Operations in MMC Mode.................................................................................. 967
26.6.1 Operation in Read Sequence............................................................................... 991
26.6.2 Operation in Write Sequence .............................................................................. 991