HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 141

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.3.2
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and
selects the rounding mode. Do not set the SZ and PR bits to 1 simultaneously; this setting is
reserved.
Initial value:
Initial value:
Bit
31 to 22 —
21
20
19
18
R/W:
R/W:
Bit:
Bit:
Floating-Point Status/Control Register (FPSCR)
Bit Name
FR
SZ
PR
DN
R/W
31
15
R
0
0
-
R/W
30
14
-
R
0
0
Cause
R/W
29
13
Initial Value
All 0
0
0
0
1
R
0
0
-
R/W
28
12
R
0
0
-
R/W
27
11
R
0
0
-
R/W
R/W
R
R/W
R/W
R/W
R/W
26
10
R
0
0
-
Enable
R/W
25
R
-
0
9
0
1: Denormalized number is treated as zero
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
Precision Mode
0: Floating-point instructions are executed as
1: Floating-point instructions are executed as
Denormalization Mode
0: Denormalized number is treated as such
pair (64 bits)
single-precision operations
double-precision operations (graphics support
instructions are undefined)
XF0 to XF15 and FPR0_BANK1 to
FPR15_BANK1 are assigned to FR0 to FR15
FR0 to FR15 and FPR0_BANK1 to
FPR15_BANK1 are assigned to XF0 to XF15
R/W
24
R
0
8
0
-
R/W
23
R
0
7
0
-
R/W
Rev. 2.00 Feb. 12, 2010 Page 57 of 1330
22
R
0
6
0
-
R/W
R/W
FR
21
0
5
0
Flag
R/W
R/W
SZ
20
0
4
0
R/W
R/W
PR
19
0
3
0
REJ09B0554-0200
R/W
R/W
DN
18
1
2
0
RM1
R/W
R/W
17
0
1
0
Cause
RM0
R/W
R/W
16
0
0
1