HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 62

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 6.9
Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................ 133
Figure 6.11 Operation of LDTLB Instruction............................................................................ 135
Figure 6.12 Memory-Mapped ITLB Address Array.................................................................. 144
Figure 6.13 Memory-Mapped ITLB Data Array 1 .................................................................... 145
Figure 6.14 Memory-Mapped ITLB Data Array 2 .................................................................... 146
Figure 6.15 Memory-Mapped UTLB Address Array ................................................................ 147
Figure 6.16 Memory-Mapped UTLB Data Array 1................................................................... 148
Figure 6.17 Memory-Mapped UTLB Data Array 2................................................................... 149
Section 7 Caches
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10 Memory-Mapped IC Data Array ............................................................................ 175
Figure 7.11 Memory-Mapped OC Address Array..................................................................... 176
Figure 7.12 Memory-Mapped OC Data Array .......................................................................... 177
Figure 7.13 Store Queue Configuration..................................................................................... 178
Section 8 Exceptions
Figure 8.1
Figure 8.2
Section 9 Interrupt Controller (INTC)
Figure 9.1
Figure 9.2
Figure 9.3
Section 10 Bus State Controller (BSC)
Figure 10.1 Block Diagram of BSC .......................................................................................... 249
Figure 10.2 Correspondence between Virtual Address Space and Off-chip Memory Space .... 252
Figure 10.3 Off-chip Memory Space Allocation ....................................................................... 254
Figure 10.4 Example of RDY Sampling Timing ....................................................................... 270
Figure 10.5 Write to RTCSR, RTCNT, RTCOR, or RFCR ...................................................... 297
Figure 10.6 Basic Timing of SRAM Interface .......................................................................... 311
Figure 10.7 Example of 32-Bit Data Width SRAM Connection ............................................... 312
Rev. 2.00 Feb. 12, 2010 Page lx of lxxxii
REJ09B0554-0200
Flowchart of Memory Access Using UTLB .......................................................... 132
Configuration of Operand Cache ........................................................................... 153
Configuration of Instruction Cache ........................................................................ 154
Configuration of Write-Back Buffer ...................................................................... 162
Configuration of Write-Through Buffer................................................................. 162
Memory-Mapped IC Address Array ...................................................................... 169
Memory-Mapped IC Data Array ............................................................................ 170
Memory-Mapped OC Address Array..................................................................... 171
Memory-Mapped OC Data Array .......................................................................... 172
Memory-Mapped IC Address Array ...................................................................... 174
Instruction Execution and Exception Handling...................................................... 189
Example of General Exception Acceptance Order................................................. 190
Block Diagram of INTC......................................................................................... 222
Example of IRL Interrupt Connection.................................................................... 236
Interrupt Operation Flowchart................................................................................ 244