HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 405

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 10.16 Example of Correspondence between SH7760 and Synchronous DRAM
(3) Burst Read
The timing chart for a burst read is shown in figure 10.16. The example below assumes that two
512k × 16-bit × 2-bank synchronous DRAMs are connected, and a 32-bit data width is used. The
burst length is 4. An ACTV command is output in the Tr cycle and then a READ command is
issued in the Tcl cycle. After 4 cycles, a READA command is issued and the read data is fetched
on the rising edge of the off-chip command clock (CKIO) from cycle Td1 to cycle Td8. The Tpc
cycle is used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM, and no new access commands can be issued to the same bank during this
waiting period. In this LSI, the number of Tpc cycles is determined based on the bits TPC2 to
TPC0 in MCR that are specified, and no commands are issued for the synchronous DRAM during
this period.
The example in figure 10.16 shows the basic cycle. To connect slower synchronous DRAM,
setting bits WCR2 and MCR can extend the cycle. The bits RCD1 and RCD0 in MCR can be used
to specify the number of cycles from the ACTV command output cycle Tr to the READ command
output cycle Tc1, with the values of 0 to 3 corresponding to 2 to 4 cycles, respectively. For 2 or
more cycles, a Trw cycle, which issues an NOP command for the synchronous DRAM, is inserted
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Pin of SH7760
Address Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
Not used
Not used
RAS Cycle
A21
H/L
0
0
A9
A8
A7
A6
A5
A4
A3
A2
Not used
Not used
CAS Cycle
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Not used
Not used
DRAM Address
Synchronous
Pin
Rev. 2.00 Feb. 12, 2010 Page 321 of 1330
Select bank address BANK
Address precharge setting
Address
Function
REJ09B0554-0200