HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1161

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
30.3.7
LDLAOR specifies the Y-coordinate increment address width used by the LCDC to read an image
recognized by the graphics driver. When the Y-coordinate is increased by 1, this register specifies
by how many bytes the address for reading data from memory should be moved, and it needs not
conform to the width of the LCD panel. This register corresponds to B when the equation Ax + By
+ C is used to calculate the memory address of a point (X, Y) in a two dimensional image.
Initial value:
Bit
15 to 10 LAO15 to
9
8
7
6 to 0
R/W:
Bit:
The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC
handles these values as longword data, the values written to the lower two bits of each
register are always treated as 0. The lower two bits of each register are always read as 0.
For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the
longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15,
or 16 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits).
LCDC Display Line Address Offset Register (LDLAOR)
LAO15
Bit Name Initial Value
LAO10
LAO9
LAO8
LAO7
LAO6
to
LAO0
R/W
15
0
LAO14
R/W
14
0
LAO13
All 0
1
0
1
All 0
R/W
13
0
LAO12
R/W
12
0
LAO11
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
LAO10
R/W
10
0
LAO9
Description
Line Address Offset
The minimum alignment unit of LDLAOR is four bytes.
Because the LCDC handles these values as longword
data, the values written to the lower two bits of the
register are always treated as 0. When reading from
the register, the lower two bits are always read as 0.
In order for VGA (640 × 480 dot) display data to be
read continuously without skipping an address
between lines, the initial value is set to (× resolution =
640). For details, see table 30.4, Display Resolutions
when Using Display Rotation, in section 30.4,
Operation.
A binary exponential at least as large as the horizontal
width of the image is recommended for the LDLAOR
value, taking into consideration the software operation
speed.
When the hardware rotation function is used, the
LDLAOR value should not correspond to the width of
the LCD panel (320 in a 320 × 240 panel), but should
be a binary exponential (in this example, 256) at least
as large as the horizontal width of the image (after
rotation, 240 in a 240 × 320 panel).
R/W
9
1
LAO8
R/W
8
0
LAO7
R/W
1
7
Rev. 2.00 Feb. 12, 2010 Page 1077 of 1330
LAO6
R/W
6
0
LAO5
R/W
5
0
LAO4
R/W
4
0
LAO3
R/W
3
0
REJ09B0554-0200
LAO2
R/W
2
0
LAO1
R/W
1
0
LAO0
R/W
0
0