HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 591

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.2.3
WTCNT and WTCSR differ from other registers in being more difficult to write to. The procedure
for writing to these registers is given below.
(1) Writing to WTCNT and WTCSR
These registers must be written to with a word transfer instruction. They cannot be written to with
a byte or longword transfer instruction.
As shown in figure 13.2, when writing to WTCNT, perform the transfer with the upper byte set to
H'5A and the lower byte containing the write data. When writing to WTCSR, perform the transfer
with the upper byte set to H'A5 and the lower byte containing the write data. This transfer
procedure writes the lower byte data to WTCNT or WTCSR.
13.3
13.3.1
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The
procedure is shown below. (As the WDT does not operate when standby mode is cleared with a
reset, the RESET pin should be held low until the clock stabilizes.)
1. Be sure to clear the TME bit in WTCSR to 0 before making a transition to software standby
2. Select the count clock to be used with bits CKS2 to CKS0 in WTCSR, and set the initial value
3. The WDT starts counting on detection of an NMI signal transition edge or an interrupt.
mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused
when the count overflows.
in WTCNT. Make these settings so that the time until the count overflows is at least as long as
the clock oscillation stabilization time. Make a transition to software standby mode, and stop
the clock, by executing a SLEEP instruction.
Notes on Register Access
Operation
Standby Clearing Procedure
WTCNT write
WTCSR write
Address: H'FFC0 000C
Address: H'FFC0 0008
(H'1FC0 000C)
(H'1FC0 0008)
Figure 13.2 Writing to WTCNT and WTCSR
15
15
H'5A
H'A5
8
8
Rev. 2.00 Feb. 12, 2010 Page 507 of 1330
7
7
Write data
Write data
REJ09B0554-0200
0
0