HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1037

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: If R2 response (17-byte command response) is requested and CTSEL0 is cleared to 0, a
26.3.10 Data Timeout Register (DTOUTR)
DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a
prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor
the data timeout. The prescaler always counts the peripheral clock, and outputs a count pulse for
every 10,000 peripheral clock cycles. The initial value of DTOUTC is 0, and DTOUTC starts
counting the prescaler output from the start of the command sequence. DTOUTC is cleared when
the command sequence has ended, or when the command sequence has been aborted by setting the
CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output.
When the command sequence does not end, DTOUTC continues counting the prescaler output,
and enters the data timeout error states when the number of prescaler outputs reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. As DTOUTC continues counting prescaler output, the DTERI flag setting condition is
repeatedly generated. To perform data timeout error handling, the command sequence should be
aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent
extra-interrupt generation.
For a command with data busy status, data timeout cannot be monitored since the command
sequence is terminated before entering the data busy state. Timeout in the data busy state should
be monitored by firmware.
Initial value:
Bit
1
0
R/W:
Bit:
timeout is generated during response reception. Therefore, set CTSEL0 to 1.
Bit
Name
CTSEL1
CTSEL0
R/W
15
1
R/W
14
1
Initial
Value
0
0
R/W
13
1
R/W
12
1
R/W
R/W
R/W
R/W
11
1
R/W
10
Description
Command Timeout Select
00: 128 transfer clock cycles from command transmission
01: 256 transfer clock cycles from command transmission
10: Setting prohibited
11: Setting prohibited
1
completion to response reception completion
completion to response reception completion
R/W
9
1
R/W
8
1
DTOUTR
R/W
7
1
Rev. 2.00 Feb. 12, 2010 Page 953 of 1330
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0554-0200
R/W
2
1
R/W
1
1
R/W
0
1