HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 42

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.7
Section 8 Exceptions ........................................................................................ 183
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Section 9 Interrupt Controller (INTC).............................................................. 221
9.1
9.2
9.3
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REJ09B0554-0200
7.6.3
7.6.4
7.6.5
Store Queues .................................................................................................................... 178
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
Exception Handling Functions......................................................................................... 183
8.1.1
8.1.2
Exception Types and Priorities ........................................................................................ 185
Exception Flow ................................................................................................................ 189
8.3.1
8.3.2
8.3.3
8.3.4
Register Descriptions ....................................................................................................... 192
8.4.1
8.4.2
8.4.3
Operation ......................................................................................................................... 195
8.5.1
8.5.2
8.5.3
8.5.4
Usage Notes ..................................................................................................................... 219
Restrictions ...................................................................................................................... 220
8.7.1
Features............................................................................................................................ 221
Input/Output Pins ............................................................................................................. 223
Register Descriptions ....................................................................................................... 223
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
OC Address Array .............................................................................................. 175
OC Data Array .................................................................................................... 177
Summary of Memory-Mapping of OC ............................................................... 178
SQ Configuration................................................................................................ 178
Writing to SQ...................................................................................................... 179
Transfer to External Memory.............................................................................. 179
Determination of SQ Access Exception.............................................................. 180
Reading from SQ ................................................................................................ 181
Exception Handling Flow ................................................................................... 183
Exception Handling Vector Addresses ............................................................... 184
Exception Flow ................................................................................................... 189
Exception Source Acceptance............................................................................. 190
Exception Requests and BL Bit .......................................................................... 191
Return from Exception Handling........................................................................ 191
Exception Event Register (EXPEVT)................................................................. 193
Interrupt Event Register (INTEVT) .................................................................... 193
TRAPA Exception Register (TRA) .................................................................... 194
Resets.................................................................................................................. 195
General Exceptions ............................................................................................. 200
Interrupts............................................................................................................. 214
Priority Order with Multiple Exceptions............................................................. 218
Restrictions on First Instruction in Exception Handling Routine ....................... 220
Interrupt Priority Level Setting Registers A to D (IPRA to IPRD)..................... 225
Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C).. 226
Interrupt Control Register (ICR)......................................................................... 227
Interrupt Source Registers 00, 04 (INTREQ00, INTREQ04) ............................. 229
Interrupt Mask Registers 00, 04 (INTMSK00, INTMSK04).............................. 231