HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1087

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: * The external device can write to these bits via the MFI only when the MFI-RS pin is 1. The
27.3.2
The MFIGSR is a 32-bit register which an MFI-connected external device uses to indicate its
status to the on-chip CPU and vice versa. When the MFI-RS pin is driven high, this register is
read-only via the MFI. To write to the MFIGSR from the MFI, specify MFIGSR setting bits
REG5 to REG0, drive the MFI-RS pin low and then perform writing. In this state, the MFIGSR
can also be read.
Initial value:
Initial value:
Bit
1
0
R/W:
R/W:
Bit:
Bit:
on-chip CPU cannot write to these bits.
MFI General Status Register (MFIGSR)
Bit
Name
BYTE1
BYTE0
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
Initial
Value
0
0
29
13
R
R
0
0
-
-
28
12
R
R
0
0
-
-
R/W
R/W*
R/W*
27
11
R
R
0
0
-
-
26
10
R
0
R
0
-
-
Description
Specifies byte position for on-chip register.
Specifies which 8 or 16 bits of the 32-bit register are to be
accessed.
•
00: Register bits 31 to 24
01: Register bits 23 to 16
10: Register bits 15 to 8
11: Register bits 7 to 0
•
00: Register bits 7 to 0
01: Register bits 15 to 8
10: Register bits 23 to 16
11: Register bits 31 to 24
However, with MFIDATA selected by bits REG5 to REG0,
each time reading from or writing to MFIDATA from the
external device occurs, bits BYTE1 and BYTE0 change
according to the following rules.
8-bit bus:
16-bit bus: 00
MFISCR.BO = 0
MFISCR.BO = 1
25
8-bit bus
8-bit bus
R
-
R
0
9
0
-
24
R
R
0
8
0
-
-
00
TUS7
STA
R/W
23
R
0
0
7
-
Rev. 2.00 Feb. 12, 2010 Page 1003 of 1330
01
10
TUS6
STA
R/W
22
R
0
6
0
-
TUS5
10
00
STA
R/W
21
R
0
5
0
-
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
16-bit bus
Register bits 31 to 16
Register bits 15 to 0
16-bit bus
Register bits 15 to 0
Register bits 31 to 16
TUS4
11
10... etc.
STA
R/W
20
R
0
0
4
-
TUS3
STA
R/W
00
19
R
0
3
0
-
REJ09B0554-0200
TUS2
STA
R/W
01... etc.
18
R
0
2
0
-
TUS1
STA
R/W
17
R
0
1
-
0
TUS0
STA
R/W
16
R
0
0
-
0