HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 751

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.3.1
Initial value:
Initial value:
Bit
31 to 4
3
2
1
R/W:
R/W:
Bit:
Bit:
Slave Control Register (ICSCR)
Bit Name
⎯
SDBS
SIE
GCAE
31
15
R
R
0
0
-
-
30
14
R
R
-
-
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R
R/W
R/W
R/W
R/W
26
10
R
R
-
0
-
0
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Slave Data Buffer Select
This bit is used to select the data buffer. The data
buffer has two modes; the FIFO buffer mode and
the single buffer mode.
Clearing SDBS to 0 will select the FIFO buffer
mode. In the receive mode, while the RDF flag is 1
with the receive byte count stored in the FIFO
buffer equal to or greater than the byte count
specified by RTRG3 to RTRG0, SCL is held low.
Reading the receive data from the FIFO buffer will
clear the RDF flag to 0 and release SCL from low
level.
Setting SDBS to 1 will select the single buffer
mode.
SCL will be held low from the moment the receive
data register receives a data packet until SDR is
cleared to 0.
0: FIFO buffer mode
1: Single buffer mode
Slave Interface Enable
Ensure to set this bit to 1 to have the slave to
operate. If this bit is low, the slave interface is
reset.
General Call Acknowledgement Enable
Ensure to set this bit to 1 when the master
requires the slave to acknowledge a transmission
of a general call address.
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
Rev. 2.00 Feb. 12, 2010 Page 667 of 1330
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
20
Section 19 I
R
R
0
4
0
-
-
SDBS
R/W
19
R
0
3
0
-
REJ09B0554-0200
R/W
SIE
18
R
0
2
0
-
2
C Bus Interface
GCAE FNA
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-