HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 993

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Section 25 Audio Codec Interface (HAC)
Section 25 Audio Codec Interface (HAC)
The HAC, the audio codec digital controller interface, supports bidirectional data transfer
compliant with Audio Codec 97 (AC'97) Version 2.1. The HAC provides serial transmission to
/reception from the AC97 codec. Each channel of the HAC can be connected to a single audio
codec device.
The HAC carries out data extraction from/insertion into audio frames. For data slots within both
receive and transmit frames, the PIO transfer by the CPU or the DMA transfer by the DMAC can
be used.
25.1
Features
The HAC has the following features:
• Digital interface to a single AC'97 version 2.1 Audio Codec
• PIO transfer of status slots 1 and 2 in Rx frames
• PIO transfer of command slots 1 and 2 in Tx frames
• PIO transfer of data slots 3 and 4 in Rx frames
• PIO transfer of data slots 3 and 4 in Tx frames
• Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Rx frames
• Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Tx frames
• Accommodates various sampling rates by qualifying slot data with tag bits and monitoring the
Tx frame request bits of Rx frames
• Generates data ready, data request, overrun and underrun interrupts
• Supports cold reset, warm reset, and power-down mode
Rev. 2.00 Feb. 12, 2010 Page 909 of 1330
REJ09B0554-0200

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