HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 787

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.6.5
Operation example:
1. Set the clock rate to ICCCR.
2. Set the slave address, etc. to ICMAR.
3. Set the RDF trigger value to ICFCR.
4. ICMCR=H'0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0. (At this point, the slave address
5. Wait for MAT, and clear ESG.
6. Wait for RDF, and read the data received from ICRXD.
7. Wait for RDF, and set FSB to 1.
8. Wait for one bit period after setting RDF to 1 and read the data received from ICRXD.
9. ICFSR=H'0000 0000 (Clear the flag.)
19.7
19.7.1
For the STOP operation in I
Single buffer mode assumes to carry out a predefined number of byte transfers. The current circuit
fetches the value of the FSB bit when the last bit of one byte is transmitted or received, and
proceeds to the STOP operation. Consequently, to stop communications after the transfer of a
specified number of bytes, the FSB bit should be set to 1 before the last byte is transferred.
This timing, however, contains a problem. In transmission mode, FSB is set to 1 BEFORE an
ACK/NACK to the last byte is checked. For this, the following software actions are required.
• Software Actions
(Repeat)
Verify that RDF is 0.
(If RDF is 1, read the data from ICRXD and then clear RDF to 0.)
is output onto I
ICFSR=H'0000 0000 (clear the flag)
The FSB bit must be set before the last eight bits are transmitted or received as mentioned
above. In the case of transmission, ACK/NACK to the last byte needs to be checked. For
example, the software should operate as follows.
Master Receiver (FIFO Buffer Mode)
Usage Notes
Restriction 1
2
C bus.)
2
C master mode, there is a timing restriction on FSB setting.
Rev. 2.00 Feb. 12, 2010 Page 703 of 1330
Section 19 I
REJ09B0554-0200
2
C Bus Interface