HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 372

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 288 of 1330
REJ09B0554-0200
Bit
9
8
7
6
5
4
3
2
Bit
Name
⎯
SZ1
SZ0
AMXEXT
AMX2
AMX1
AMX0
RFSH
Initial
Value
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Memory Data Size
These bits specify the bus width of synchronous DRAM.
This setting has priority over the BCR2 register setting.
00:
01:
10:
11:
Address Multiplexing
These bits specify address multiplexing for synchronous
DRAM. For details, refer to appendix D, Address
Multiplexing for Synchronous DRAM.
0000:
1000:
0001:
1001:
0010:
0011:
0100:
0101:
0110:
1110:
0111
Other settings are prohibited.
Refresh Control
Specifies refresh control. Selects whether refreshing is
performed for synchronous DRAM. When the refresh
function is not used, the refresh request cycle generation
timer can be used as an interval timer.
0: Refresh is not performed
1: Refresh is performed
Synchronous DRAM
Setting prohibited
Setting prohibited
Setting prohibited
32 bits
(512k × 16 bits × 2) × 2
(512k × 16 bits × 2) × 2
(1M × 8 bits × 2) × 4
(1M × 8 bits × 2) × 4
(1M × 16 bits × 4) × 2
(2M × 8 bits × 4) × 4
(512k × 32 bits × 4) × 1
(1M × 32 bits × 2) × 1
(4M × 4 bits × 4) × 8
(4M × 16 bits × 4) × 2
(256k × 32 bits × 2) × 1
Synchronous DRAM structure
example
Bank
a[21]*
a[20]*
a[22]*
a[21]*
a[23:22]*
a[24:23]*
a[22:21]*
a[22]*
a[25:24]*
a[25:24]*
a[20]*
3
3
3
3
3
3
3
3
3
3
3