HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 599

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.2.2
STBCR2 is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode
transition conditions.
Bit
4
3
2
1, 0
Bit
7
Bit Name
MSTP4
⎯
MSTP2
⎯
Bit Name
DSLP
Standby Control Register 2 (STBCR2)
Initial value:
Initial Value R/W
0
0
0
All 0
Initial value
0
R/W:
Bit:
DSLP STHZ
R/W
7
0
R/W
6
0
R/W
R
R/W
R
R/W
R/W
R
5
0
-
Description
Module Stop 4
Specifies stopping of the clock supply to the
DMAC among the peripheral modules. When DMA
transfer is used, stop the transfer before setting
this bit to 1. When DMA transfer is performed after
clearing this bit to 0, DMAC settings must be
made again.
0: DMAC operates
1: DMAC clock supply is stopped
Reserved
This bit is always read as 0. The write value
should always be 0.
Module Stop 2
Specifies stopping of the clock supply to the TMU
among the peripheral modules.
0: TMU operates
1: TMU clock supply is stopped
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Deep Sleep
Specifies a transition to deep sleep mode
0: Transition to sleep mode or standby mode on
1: Transition to deep sleep mode on execution of
4
0
R
-
execution of SLEEP instruction, according to
setting of the STBY bit in STBCR
SLEEP instruction when the STBY bit in
STBCR is 0.
R
3
0
-
Rev. 2.00 Feb. 12, 2010 Page 515 of 1330
R
2
-
0
MSTP6 MSTP5
R/W
1
0
R/W
0
0
REJ09B0554-0200