HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 331

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The BSC divides the off-chip memory space and outputs control signals complying with
specifications of various types of memory and bus interfaces. It enables the connection of
synchronous DRAM, SRAM, ROM, etc., to this LSI. It also supports the PCMCIA interface
protocol, which implements simplified system design and high-speed data transfers by a compact
system.
10.1
The BSC has the following features:
• Divides the off-chip memory space into seven areas for management.
• SRAM interface
• Synchronous DRAM interface
⎯ Maximum 64 Mbytes for each of areas 0 to 6
⎯ Bus width of each area can be controlled by register settings (except area 0, which uses an
⎯ Wait-cycle insertion by RDY pin
⎯ Wait-cycle insertion can be controlled by program
⎯ Types of memory are specifiable for connection to each area
⎯ Output the control signals of memory to each area
⎯ Automatic wait cycle insertion to prevent data bus collisions in case of consecutive
⎯ Write strobe setup time and hold time periods can be inserted in a write cycle to enable
⎯ Wait-cycle insertion can be controlled by program
⎯ Wait-cycle insertion by RDY pin
⎯ Connectable areas: 0 to 6
⎯ Settable bus widths: 32, 16, 8
⎯ Row address/column address multiplexing according to synchronous DRAM capacity
⎯ Burst operation
⎯ Auto-refresh and self-refresh
⎯ Synchronous DRAM control signal timing can be controlled by register settings
⎯ Consecutive accesses to the same row address
⎯ Connectable areas: 2, 3
⎯ Settable bus width: 32
off-chip pin setting)
memory accesses to different areas, or a read access followed by a write access to the same
area
connection to low-speed memory
Features
Section 10 Bus State Controller (BSC)
Rev. 2.00 Feb. 12, 2010 Page 247 of 1330
REJ09B0554-0200