HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 334

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Name
Address bus
Data bus
Bus cycle start
Chip select 6 to 0
Read/write
Row address
strobe
Read/column
address strobe/
cycle frame
Data enable 0
Data enable 1
10.2
Table 10.1 shows the BSC pin configuration.
Table 10.1 Pin Configuration
Rev. 2.00 Feb. 12, 2010 Page 250 of 1330
REJ09B0554-0200
Input/Output Pins
Signals
A25 to A0
D31 to D0
BS
CS6 to CS0
RD/WR
RAS
RD/CASS/
FRAME
WE0/
DQM0/
REG
WE1/
DQM1
I/O
Output Address output
Input/
Output
Output Signal that indicates the start of a bus cycle
Output Chip select signals that indicate the area being
Output Data bus input/output direction designation signal
Output RAS signal when setting synchronous DRAM
Output Strobe signal that indicates a read cycle
Output When setting PCMCIA interface: REG signal
Output When setting PCMCIA interface: write strobe signal
Description
Data input/output
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
Also used as the DRAM/PCMCIA interface write
designation signal
interface
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
When setting SRAM interface: write strobe signal for
D7 to D0
When setting synchronous DRAM interface:
selection signal for D7 to D0
When setting SRAM interface: write strobe signal for
D15 to D8
When setting synchronous DRAM interface:
selection signal for D15 to D8