HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 908

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.6
CANTECREC is 16 bit read/(write) register and consists of the transmit error counter (TEC) and
receive error counter (REC) that function as a counter indicating the number of transmit/receive
message errors on the CAN interface. The counter value is stipulated in CAN Specification
Version 2.0, Robert Bosch GmbH, 1991 and Implementation Guide for the CAN Protocol, CAN
Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany. In the normal mode, this
register is read-only and can only be modified by the CAN interface. This register can be cleared
by a Reset request (MCR0) or Bus off.
Initial value:
Note: * It is possible to write the value only in test mode with MCR15 = MCR14 = 1.
Rev. 2.00 Feb. 12, 2010 Page 824 of 1330
REJ09B0554-0200
Bit
15, 11,
10
14 to
12, 9 to
0
Bit
15 to 8
7 to 0
R/W:
Bit:
Bit Name
⎯
IMR14 to
IMR12,
IMR9 to
IMR0
Transmit Error Counter and Receive Error Counter (CANTECREC)
Bit Name
TEC7 to
TEC0
REC7 to
REC0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
R/W* R/W*
15
0
14
0
R/W*
13
0
Initial Value
All 1
All 1
Initial Value
All 0
All 0
R/W*
12
0
R/W* R/W*
11
0
R/W
R
R/W
R/W
R/W*
R/W*
10
0
R/W*
9
0
Description
Reserved
The write value should always be 1. The read
value is not guaranteed.
to IRR12, IRR9 to IRR0. When the bit is set, the
interrupt is masked, however, the CANIRR bit
setting is retained.
0: Corresponding CANIRR bit is not masked (IRQ
1: Corresponding interrupt of CANIRR bit is
Description
Transmit error counter
Receive error counter
Masks interrupt sources corresponding to IRR14
R/W*
8
0
is generated for interrupt conditions).
masked.
R/W* R/W*
7
0
6
0
R/W*
5
0
R/W*
4
0
R/W* R/W*
3
0
2
0
R/W*
1
0
R/W*
0
0