HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 560

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6.8
There are two types of transfer end interrupts.
• A0TXH, A0RXH, A1TXH, or A1RXH (half data transfer end interrupt)
• A0TXE, A0RXE, A1TXE, or A1RXE (all data transfer end interrupt)
Using half data transfer end and all data transfer end interrupts makes transfers for consecutive
audio data efficient since half of the transmit/receive buffer can be accessed by the CPU during a
transfer of the other half.*
In addition, by enabling the auto reload function (TAR/RAR bit in DMAACR), it is not necessary
to re-specify the registers for the second transfer or later.
Notes: 1. When the transfer size specified in DMAARXTCR or DMAATXTCR is 4 bytes, a half
11.6.9
Data is transferred between the HAC or SSI and a transmit/receive buffer in 32-bit (longword)
units. When data less than 32 bits is transferred, the byte order of audio data in the
transmit/receive buffer in synchronous DRAM may differ from the DMA transfer order,
depending on the MD5 pin level which specifies the endian type.
Rev. 2.00 Feb. 12, 2010 Page 476 of 1330
REJ09B0554-0200
An interrupt is generated when a half of the transfer size specified by DMAARXTCR or
DMAATXTCR is completed.*
An interrupt is generated when the whole transfer size specified by DMAARXTCR or
DMAATXTCR is completed.
2. When the transfer size specified in DMAARXTCR or DMAATXTCR is 8n + 4 bytes
3. The DMABRG for the HAC or SSI has FIFOs that stores a maximum of 64-byte data
Double Buffer Control for Audio Data
HAC/SSI Endian Conversion Function
data transfer end interrupt is not generated.
(n is an integer = 1 or greater) (transfer count is an odd number), a half data transfer
end interrupt is generated when n + 1 transfers are completed.
that is pre-fetched on transmit. If a half of the transfer size of audio data is less than 64
bytes, the remaining data in the transmit/receive buffer may already be stored in the
FIFO when a half data transfer end interrupt is generated. When using the double
buffer control by a half data transfer end interrupt, configure the transmit/receive buffer
in synchronous DRAM having the size of 128 bytes or more.
3
1
*
2