HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 169

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. Incorrect data may be written to the operand cache when the following three conditions occur
3. The ITLB hit judgment may be incorrect when the following three conditions occur at the
4. Incorrect data may be written to an FPU-related register (FR0 to FR15, XF0 to XF15, FPSCR,
Note: The number of instructions following the instructions mentioned above that may be
c. The four words of data following the TRAPA instruction or undefined instruction code
at the same time.
a. The operand cache is enabled (CCR.OCE = 1).
b. Undefined instruction code H'FFFD is executed.
c. The four words of data following the undefined instruction code H'FFFD mentioned in b.
same time. If an ITLB hit is erroneously judged to be a miss, ITLB re-registration is
performed. This can cause an ITLB multi-hit exception to occur.
a. The MMU enabled (MMUCR.AT = 1).
b. A TRAPA instruction or undefined instruction code H'FFFD in a TLB conversion area
c. The four words of data following the TRAPA instruction or undefined instruction code
or FPUL) or to the MACH or MACL register when the following two conditions occur at the
same time.
a. A TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
b. The eight words of data following the TRAPA instruction, SLEEP instruction, or undefined
H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access
(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or
internal TLB.
contain code that can be interpreted as an OCBI, OCBP, OCBWB, or TAS.B instruction
accessing an address (H'E0000000 to H'E3FFFFFF) mapped to the internal store queue.
(area U0, P0, or P3) is executed.
H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access
(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or
internal TLB.
executed
instruction code H'FFFD mentioned in a. contain H'Fxxx (an instruction with H'F as the
first four bits), excluding H'FFFD, and the code can be interpreted, in combination with
FPSCR.PR at that point, as an undefined instruction.
Example: Instruction H'FxxE (x: any hexadecimal digit) is defined here as undefined when
FPSCR.PR is set to 1.
affected by the problem is as follows: in the case of 1. to 3., the number of instructions
that can be executed in 2xIck, and in the case of 4., the number of instructions that can be
executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or
4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in
“the four words (or eight words) of data following the instruction.”
Rev. 2.00 Feb. 12, 2010 Page 85 of 1330
REJ09B0554-0200