HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1218

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. The operation when a break condition is satisfied depends on the BL bit in SR of the CPU.
4. When sequential condition mode has been selected and the channel B condition is matched
31.3.4
1. When an instruction access/read/word setting is made in BBRA/BBRB, an instruction access
2. When a pre-execution break is specified, the break is effected when it is confirmed that the
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REJ09B0554-0200
When the BL bit is 0, exception handling is started and the condition match flag
(CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is
1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched
condition but exception handling is not started.
The condition match flags (CMFA, CMFB) are set by a break condition match, but are not
automatically reset. Therefore, a memory store instruction should be used on BRCR to clear
the flags to 0. For details of the exact setting conditions for the condition match flags, see
section 31.3.6, Condition Match Flag Setting.
after the channel A condition has been matched, a break is effected at the instruction at which
the channel B condition was matched. For details of the operation when the channel A
condition match and channel B condition match occur close together, see section 31.3.8,
Contiguous A and B Settings for Sequential Conditions. With sequential conditions, only the
channel B condition match flag is set. To clear the channel A match when the channel A
condition has been matched but the channel B condition has not yet been matched in sequential
condition mode, B'0 should be written to the SEQ bit in BRCR.
cycle can be used as a break condition. In this case, breaking before or after execution of the
relevant instruction can be selected with the PCBA/PCBB bit in BRCR. When an instruction
access cycle is used as a break condition, clear the LSB of BARA/BARB to 0. A break will not
be generated if this bit is set to 1.
instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an
instruction that is fetched but not executed when a branch or exception occurs) cannot be used
in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of
the fetch of an instruction subject to a break, the break exception handling is carried out first.
The instruction TLB exception handling is performed when the instruction is re-executed (see
section 8.2, Exception Types and Priorities). Also, since a delayed branch instruction and the
delay slot instruction are executed as a single instruction, if a pre-execution break is specified
for a delay slot instruction, the break will be effected before execution of the delayed branch
instruction. However, a pre-execution break cannot be specified for the delay slot instruction
for an RTE instruction.
Instruction Access Cycle Break