HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 549

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
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Transfer Condition
Transfer source: external memory
Transfer destination: external device with DACK
Number of transfers: 32
Transfer source address: decremented
Transfer destination address: (setting invalid)
Transfer request source: external pin (DREQ1)
edge detection
Bus mode: burst
Transfer unit: word
No interrupt request at end of transfer
External request 2-channel mode
Channel priority order: 2 > 0 > 1 > 3 > 4 > 5 > 6 > 7
11.5
11.5.1
(1) External Request 2-Channel Mode
Examples of transfer of data in external memory to an external device with DACK using DMAC
channel 1 in external request 2-channel mode are considered here.
Table 11.11 (1) shows the transfer conditions and the corresponding register settings.
Table 11.11 (1) Conditions for Transfer between External Memory and External Device
Note: * When DREQ1 is specified as a DMA transfer request source in external request 2-channel
mode, only channel 1 accepts the DMA transfer request (DREQ0 is accepted only by
channel 0).
Examples of Use
Examples of Transfer between External Memory and an External Device with
DACK
with DACK, and Corresponding Register Settings
Register
SAR1
DAR1
DMATCR1
CHCR1
DMAOR
Rev. 2.00 Feb. 12, 2010 Page 465 of 1330
Setting
H'0C00 0000
(Accessed by DACK)
H'0000 0020
H'0000 22A5*
H'0000 0201
REJ09B0554-0200

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