HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 49

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
19.1 Features ............................................................................................................................ 663
19.2 Input/Output Pins ............................................................................................................. 664
19.3 Register Descriptions ....................................................................................................... 664
19.4 Operation.......................................................................................................................... 688
19.5 FIFO Mode Operation...................................................................................................... 697
19.6 Programming Examples ................................................................................................... 698
19.7 Usage Notes ..................................................................................................................... 703
19.3.1 Slave Control Register (ICSCR) ......................................................................... 667
19.3.2 Slave Status Register (ICSSR) ............................................................................ 668
19.3.3 Slave Interrupt Enable Register (ICSIER) .......................................................... 671
19.3.4 Slave Address Register (ICSAR) ........................................................................ 672
19.3.5 Master Control Register (ICMCR)...................................................................... 672
19.3.6 Master Status Register (ICMSR) ........................................................................ 675
19.3.7 Master Interrupt Enable Register (ICMIER)....................................................... 677
19.3.8 Master Address Register (ICMAR) .................................................................... 678
19.3.9 Clock Control Register (ICCCR) ........................................................................ 679
19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD)........................................... 680
19.3.11 FIFO Control Register (ICFCR) ......................................................................... 682
19.3.12 FIFO Status Register (ICFSR) ............................................................................ 684
19.3.13 FIFO Interrupt Enable Register (ICFIER) .......................................................... 686
19.3.14 Receive FIFO Data Count Register (ICRFDR)................................................... 687
19.3.15 Transmit FIFO Data Count Register (ICTFDR) ................................................. 687
19.4.1 Data and Clock Filters......................................................................................... 688
19.4.2 Clock Generator .................................................................................................. 688
19.4.3 Master and Slave Interfaces ................................................................................ 688
19.4.4 Software Status Interlocking............................................................................... 688
19.4.5 I
19.4.6 7-Bit Address Format.......................................................................................... 691
19.4.7 10-Bit Address Format........................................................................................ 692
19.4.8 Master Transmit Operation (Single Buffer Mode).............................................. 693
19.4.9 Master Receiver Operation (Single Buffer Mode) .............................................. 695
19.4.10 Standby Mode ..................................................................................................... 697
19.5.1 Master Transmitter Operation (FIFO Buffer Mode) ........................................... 697
19.5.2 Master Receiver Operation (FIFO Buffer Mode)................................................ 698
19.6.1 Master Transmitter (Single Buffer Mode) .......................................................... 698
19.6.2 Master Receiver (Single Buffer Mode)............................................................... 700
19.6.3 Master Transmitter—Restart—Master Receiver (Single Buffer Mode) ............. 701
19.6.4 Master Transmitter (FIFO Buffer Mode) ............................................................ 702
19.6.5 Master Receiver (FIFO Buffer Mode) ................................................................ 703
19.7.1 Restriction 1 ........................................................................................................ 703
2
2
C Bus Data Format ........................................................................................... 690
C Bus Interface .............................................................................663
Rev. 2.00 Feb. 12, 2010 Page xlvii of lxxxii
REJ09B0554-0200