HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 504

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.16 DMA Audio Receive Transfer Counter (DMAARXTCNT)
DMAARXTCNT is a 32-bit read-only register that indicates the number of remaining bytes of
transfer bytes specified by DMAARXTCR. This register is write-prohibited. DMAARXTCNT0
corresponds to HAC(0) or SSI(0) and DMAARXTCNT1 corresponds to HAC(1) or SSI(1).
Writing 1 to the RDE bit in DMAACR sets the DMAARXTCR value in this register. On forced
termination, the number of transfer bytes remaining at that time is indicated.
Initial value:
Initial value:
11.3.17 DMA USB Source Address Register (DMAUSAR)
DMAUSAR is a 32-bit readable/writable register that specifies the source address of a DMA
transfer. The settings in this register are valid only for the DMA transfer between the USB internal
shared memory (hereafter referred to as shared memory) and synchronous DRAM. During USB
DMA transfer, the register value can be read but cannot be modified. The address should be
specified as a 32-bit boundary.
Specify this register value as a synchronous DRAM address for a DMA transfer from synchronous
DRAM to the shared memory, and as a shared memory address for a transfer from the shared
memory to synchronous DRAM. In the case of a transfer from the shared memory to synchronous
DRAM, the address should be within the transfer source, that is the shared memory area (H'FE34
1000 to H'FE34 2FFC). When an address outside of this area is specified, the DMAC detects a
USB address error and terminates the USB DMA transfer.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 420 of 1330
REJ09B0554-0200
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
31
15
31
15
R
R
0
0
-
-
R/W
R/W
30
14
30
14
R
R
0
0
-
-
R/W
R/W
29
13
29
13
R
R
0
0
-
-
R/W
R/W
28
12
28
12
R
R
0
0
-
-
R/W
R/W
27
11
27
11
R
R
0
0
-
-
R/W
R/W
26
10
26
10
R
R
0
0
-
-
R/W
R/W
25
25
R
R
9
0
9
0
-
-
R/W
R/W
24
24
R
R
0
0
8
8
-
-
R/W
R/W
23
23
R
R
7
0
7
0
-
-
R/W
R/W
22
22
R
R
0
0
6
6
-
-
R/W
R/W
21
21
R
R
0
0
5
5
-
-
R/W
R/W
20
20
R
R
4
0
4
0
-
-
R/W
R/W
19
19
R
R
-
3
-
0
3
0
R/W
R/W
18
18
R
R
2
0
2
0
-
-
R/W
17
17
R
R
R
-
1
-
0
1
0
R/W
16
16
R
R
R
0
0
0
0
-
-