HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 69

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 20.9 Basic Sample Format (Transmit Mode with Example System/Data Word
Length) ...................................................................................................................728
Figure 20.10 Inverted Clock ........................................................................................................729
Figure 20.11 Inverted Word Select.............................................................................................. 729
Figure 20.12 Inverted Padding Polarity .......................................................................................729
Figure 20.13 Padding Bits First, Followed by Serial Data, with Delay.......................................730
Figure 20.14 Padding Bits First, Followed by Serial Data, without Delay..................................730
Figure 20.15 Serial Data First, Followed by Padding Bits, without Delay..................................730
Figure 20.16 Parallel Right Aligned with Delay .........................................................................731
Figure 20.17 Mute Enabled .........................................................................................................731
Figure 20.18 Compressed Data Format, Master Transmitter, Burst Mode Disabled...................732
Figure 20.19 Compressed Data Format, Master Transmitter, and Burst Mode Enabled .............732
Figure 20.20 Transition Diagram between Operation Modes......................................................734
Figure 20.21 Transmission Using DMA Controller ....................................................................736
Figure 20.22 Transmission using Interrupt Data Flow Control ...................................................737
Figure 20.23 Reception using DMA Controller ..........................................................................739
Figure 20.24 Reception using Interrupt Data Flow Control ........................................................740
Figure 20.25 Slave Mode SSI Transfer Termination/Restart Timing..........................................742
Section 21 USB Host Module (USB)
Figure 21.1 Block Diagram of USB Host Module.....................................................................744
Figure 21.2 Memory Map of Shared Memory...........................................................................782
Figure 21.3 USB Read Operation ..............................................................................................783
Figure 21.4 Example of Transfer Failure...................................................................................783
Figure 21.5 Example of RHSC Interrupt Handling ...................................................................784
Section 22 Controller Area Network 2 (HCAN2)
Figure 22.1 Block Diagram of HCAN2 Module........................................................................786
Figure 22.2 HCAN2 Memory Map............................................................................................789
Figure 22.3 Mailbox N Structure...............................................................................................792
Figure 22.4 Acceptance Filter....................................................................................................797
Figure 22.5 Reset Sequence.......................................................................................................841
Figure 22.6 Transmission Request.............................................................................................842
Figure 22.7 Internal Arbitration for Transmission.....................................................................843
Figure 22.8 Message Receive Sequence....................................................................................845
Figure 22.9 Changing ID of Receive Box or Changing Receive Box to Transmit Box ............847
Section 23 Serial Protocol Interface (HSPI)
Figure 23.1 Block Diagram of HSPI .........................................................................................850
Figure 23.2 Operational Flowchart............................................................................................861
Figure 23.3 Timing Conditions when FBS = 0..........................................................................863
Figure 23.4 Timing Conditions when FBS = 1..........................................................................864
Rev. 2.00 Feb. 12, 2010 Page lxvii of lxxxii
REJ09B0554-0200