HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1090

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

27.3.4
The MFIMCR is a 32-bit register that the external device uses to control the MFRAM via the
MFI.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1006 of 1330
REJ09B0554-0200
Bit
31 to 8
7
6
5
R/W:
R/W:
Bit:
Bit:
MFI Memory Control Register (MFIMCR)
31
15
Bit
Name
⎯
LOCK
⎯
WT*
R
R
0
0
-
-
3
30
14
-
R
-
R
0
0
Initial
Value
All 0
0
0
0
29
13
R
R
0
0
-
-
28
12
R
R
0
0
-
-
R/W
R
R/W*
R
R/W*
27
11
R
0
R
0
-
-
1
1
26
10
R
R
0
-
0
-
Description
These bits are always read as 0. The write value should
always be 0.
Lock
This bit is used to lock read/write operations during
continuous access. Writing 1 to the LOCK bit retains the
values of the RD and WT bits simultaneously set until
clearing the LOCK bit to 0. Setting both the RD and
LOCK bits simultaneously to 1 puts the MFI in the
continuous read mode; setting both the WT and LOCK
bits simultaneously to 1 results in the continuous write
mode. Do not set the RD and WT bits simultaneously to
1.
Reserved
This bit is always read as 0. The write value should
always be 0.
Write
Setting this bit to 1 writes the MFIDATA value to the
MFRAM address indicated by MFIADR.*
•
•
Reserved
Setting both the WT and LOCK bits simultaneously to
1 results in the continuous write mode and enables
high-speed data transfer *
until the WT bit is next written to 0, or until the LOCK
bit is cleared to 0.
If not setting the LOCK bit simultaneously to 1, writing
to MFRAM is performed only once. The WT bit is
automatically cleared to 0.
25
R
R
-
0
9
0
-
24
R
R
0
8
0
-
-
LOCK
R/W*
23
R
0
7
0
-
1
22
R
0
R
0
6
-
-
WT*
R/W*
21
R
0
0
5
-
3
4
1
. The WT value remains 1
20
R
0
4
0
R
-
-
RD*
R/W*
19
R
0
3
0
-
3
2
1
18
R
0
2
0
R
-
-
17
R
0
1
-
0
R
-
AI/AD
R/W*
16
R
0
0
-
0
1