HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 920

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• CANUMSR0
Initial value:
22.5.15 Timer Counter Register (CANTCNTR)
CANTCNTR is a 16-bit read/write register that allows the CPU to monitor and modify the value
of the Free Running Timer Counter. When the Timer rolls over or meets CANTCMR and TCR11
is set to 1, CANTCNTR is set to 0 and starts running again.
Initial value:
Note: * The register can be cleared by the Compare Match condition.
Rev. 2.00 Feb. 12, 2010 Page 836 of 1330
REJ09B0554-0200
15 to 0
15 to 0
15 to 0
Bit
Bit
Bit
R/W:
R/W:
Bit:
Bit:
UMSR0
UMSR1[15:0]
UMSR0[15:0]
TCNTR[15:0]
TCNTR
R/W*
R/W
_15
15
15
15
0
0
Bit Name
Bit Name
Bit Name
UMSR0
TCNTR
R/W*
R/W
_14
14
14
14
0
0
UMSR0
TCNTR
R/W*
R/W
_13
13
13
13
0
0
UMSR0
TCNTR
R/W*
All 0
All 0
All 0
R/W
_12
Initial Value
12
Initial Value
12
12
Initial Value
0
0
UMSR0
TCNTR
R/W*
R/W
_11
11
11
11
0
0
UMSR0
TCNTR
R/W*
R/W
_10
10
10
10
0
0
R/W
R/W
R/W*
UMSR0
TCNTR
R/W*
R/W
R/W
R/W
R/W
_9
9
0
9
9
0
UMSR0
TCNTR
R/W*
R/W
_8
8
8
0
8
0
Indicate that an unread received message has
been overwritten for Mailboxes 31 to 16.
0: Clearing condition: Write a 1 to this bit.
1: Unread received message is overwritten by
Indicate that an unread received message has
been overwritten for Mailboxes 15 to 0.
0: Clearing condition: Write a 1 to this bit.
1: Unread received message is overwritten by
Indicates the value of 16 bit Free Running
Timer
UMSR0
TCNTR
a new message or overrun condition.
Setting condition: A new message is
received before CANRXPR or CANRFPR is
cleared.
a new message or overrun condition.
Setting condition: A new message is
received before CANRXPR or CANRFPR is
cleared.
R/W*
R/W
_7
7
7
0
7
0
UMSR0
TCNTR
R/W*
R/W
_6
0
6
0
6
6
UMSR0
TCNTR
R/W*
R/W
_5
5
0
5
5
0
Description
Description
Description
UMSR0
TCNTR
R/W*
R/W
_4
4
0
4
4
0
UMSR0
TCNTR
R/W*
R/W
_3
3
3
0
3
0
UMSR0
TCNTR
R/W*
R/W
_2
2
0
2
0
2
UMSR0
TCNTR
R/W* R/W*
R/W
_1
1
0
1
1
0
UMSR0
TCNTR
R/W
_0
0
0
0
0
0