HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 905

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
6
5
4
Bit Name
IRR6
IRR5
IRR4
Initial Value
0
0
0
R/W
R/W
R/W
R/W
This bit is set when the HCAN2 enters the Bus-off
state or when the HCAN2 leaves Bus-off state
and returns to Error-Active. This is because that
the existing condition is that 11 recessive bits x
128 have been received at the node of TEC ≥ 256
or at the end of Bus-off. This bit remains latched
even though the HCAN2 node leaves the Bus-off
condition, and needs to be explicitly cleared by
software. The software is expected to read the
GSR0 to judge whether HCAN2 has become Bus-
off or error active, GSR0 should be read. This bit
is cleared by writing a 1. Writing a 0 has no effect.
0: Clearing condition: Write a 1 to this bit.
1: Bus off state caused by a transmit error or error
Error Passive Interrupt Flag
Indicates the Error Passive state caused by the
transmit/receive error counter. This bit is cleared
by writing a 1, while writing a 0 has no effect. If
this bit is cleared, the node may still be error
passive.
0: Clearing condition: Write a 1 to this bit.
1: Error passive state is caused by a
Receive Overload Warning Interrupt Flag
This bit becomes set and latches if the receive
error counter (REC) reaches a value greater than
96. This bit is cleared by writing a 1. Writing a 0
has no effect. When the interrupt is cleared, the
REC still holds its value greater than 96.
0: Clearing condition: Write a 1 to this bit.
1: Error warning state is caused by a receive
Description
Bus Off Interrupt Flag
active state returned from Bus-off.
Setting condition: TEC ≥ 256 or the end of bus-
off after receiving 128 x 11 bits
transmit/receive error.
Setting condition: TEC ≥ 128 or REC ≥ 128
error. Setting condition: REC ≥ 96
Rev. 2.00 Feb. 12, 2010 Page 821 of 1330
REJ09B0554-0200