HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 13

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
10.5.8 Wait Control
Register 4 (WCR4)
Table 10.9 WCR3 and
WCR4 Settings for Area
1
10.5.9 Memory
Control Register (MCR)
10.5.12 Refresh Timer
Control/Status Register
(RTCSR)
10.6.2 Areas
(5) Area 4
Page
282
283
285
294
308
Revision (See Manual for Details)
Description amended
WCR4 is a 32-bit readable/writable register that specifies the
negation period for the CS1 signal. Specifying bits CSH1 and
CSH0 can insert the negation cycles from 0 to 3. If the CS1
negate period is set, it must be set to match the WCR3 data
hold time (A1H[1:0]). If the CS1 negate period is not specified
(CSH[1:0] = 00), there is no need to match the WCR3 data
hold time (A1H[1:0]).
Table amended and note added
Note: * Only use the combinations listed in table 10.9 for the
Newly added
Table amended
Table amended
Description amended
In addition, any number of wait cycles can be inserted in each
bus cycle by the external wait pin (RDY).
Bit
30
Bit
15 to 8 ⎯
Bit
31 to 2
1
0
Bit
Name
MRSET
Bit
Name
Bit
Name
CSH1*
CSH0*
settings.
Initial
Value
All 0
0
0
Initial
Value
0
Initial
Value
All 0
R/W
R/W
R/W
R/W
R
R/W
R/W
Set this bit to 1 to make the mode register setting for
synchronous DRAM. See the description of power-on
sequence in section 10.6.4, (10) Power-On Sequence.
0: All-bank precharge
1: Mode register setting
Reserved
These bits are always read as 0.
Description
Reserved
These bits are always read as 0, and the write value
should always be 0.
CS Hold Cycle Setting
Specifies the number of wait cycles inserted during data
hold after CS1 is negated.
00:
01:
10:
11:
If a value other than 00 is set, set WCR3.A1RDH to 1.
Description
Mode Register Set
Description
Rev. 2.00 Feb. 12, 2010 Page xi of lxxxii
0
1
2
3
Wait cycles to be inserted
REJ09B0554-0200