HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 373

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. Inhibited in RAS down mode
10.5.10 PCMCIA Control Register (PCR)
PCR is a 16-bit readable/writable register that specifies the OE and WE signal assertion/negation
timing for areas 5 and 6 specified as the PCMCIA interface. The OE and WE signal assertion
width is specified by the wait control bits in WCR2.
Initial value:
Bit
1
0
R/W:
Bit:
2. Bits 29 to 27. RAS precharge period after refresh
3. a[x]: Off-chip address; not address pin
Bit
Name
RMODE
⎯
PCW1
R/W
A5
15
0
PCW0
R/W
A5
14
0
Initial
Value
0
0
PCW1
R/W
A6
13
0
PCW0
R/W
A6
12
0
R/W
R/W
R
TED2
R/W
A5
11
0
TED1
R/W
A5
10
0
Description
Refresh Mode
Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When RFSH
bit = 1 and RMODE = 0, auto-refreshing is performed for
synchronous DRAM at the interval specified in refresh-
related registers RTCNT, RTCOR, and RTCSR. If a
refresh request is issued during an off-chip bus cycle,
the refresh cycle is executed when the bus cycle ends.
When RFSH = 1 and RMODE =1, if a refresh request is
issued during an off-chip bus cycle, the synchronous
DRAM waits until the bus cycle ends before entering the
self-refresh state. All refresh requests for memory in the
self-refresh state are ignored.
0: Auto refresh (when RFSH = 1)
1: Self refresh (when RFSH = 1)
Reserved
This bit is always read as 0. The write value should
always be 0.
TED0
R/W
A5
9
0
TED2
R/W
A6
8
0
TED1
R/W
A6
7
0
Rev. 2.00 Feb. 12, 2010 Page 289 of 1330
TED0
R/W
A6
6
0
TEH2
R/W
A5
5
0
TEH1
R/W
A5
4
0
TEH0
R/W
A5
3
0
REJ09B0554-0200
TEH2
R/W
A6
2
0
TEH1
R/W
A6
1
0
TEH0
A6
R/W
0
0