HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 14

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
11.3.4 DMA Channel
Control Register
(CHCR)
11.4.4 Types of DMA
Transfer
Figure 11.6 Data Flow
in Single Address Mode
11.4.5 Number of Bus
Cycles and DREQ Pin
Sampling Timing
Figure 11.30 Single
Address Mode/Burst
Mode in DMABRG
Mode External Device
→ External Bus/DREQ
(Level Detection)/32
Byte Block Transfer
(Bus Width: 32 bits,
SDRAM: row hit write)
11.4.6 Ending DMA
Transfer
(3) Notes on Transfer
End
Rev. 2.00 Feb. 12, 2010 Page xii of lxxxii
REJ09B0554-0200
Page
396
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Revision (See Manual for Details)
Table amended
Figure amended
Figure amended
Description amended
•
Bit
3
detection)
Bus cycle
DREQ0
DREQ1
DRAK0
DACK0
A[25:0]
D[31:0]
(Level
CKIO
External requests
See item 5 in External Request Acceptance Conditions in
section 11.4.2, DMA Transfer Requests (2) External
Request Mode.
: Data flow
Bit Name
CHSET
1st
acceptance
CPU
SH7760
Initial Value
0
Asserted 2 cycles before
DMAC
start of bus cycle
D1
R/W
R/W
DREQ
D2
DACK
Destination address
D5
External
address
bus
DMAC-1
Description
Channel Setting
Since the internal state of the acceptance unit for
the corresponding channel external and DMABRG
requests are cleared when 1 is written to this bit in
DMABRG mode, write 1 to this bit when setting up
the corresponding channel. Note, however, that
this bit always reads out as 0.
Note: This operation is invalid in external request
D6
D7
D8
2-channel mode.
External
data bus
2nd
acceptance
Asserted 2 cycles before
start of bus cycle
External device
D1
Destination address
with DACK
External
memory
D2
DMAC-2
D7
D8
CPU