HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 338

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MD4
0
1
(2) Memory Bus Width
In this LSI, the memory bus width can be set independently for each area. For area 0, a bus width
of 8, 16, or 32 bits can be selected at a power-on reset by a RESET signal, using off-chip pins. The
correspondence between the off-chip pins (MD4 and MD3) and the bus width at a power-on reset
by a RESET signal is shown below.
Table 10.3 Correspondence between Off-chip Pins (MD4 and MD3) and Bus Width
When SRAM interface is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be selected by
BCR2. When burst ROM interface is used, a bus width of 8, 16, or 32 bits can be selected. When
byte control SRAM interface is used, a bus width of 16 or 32 bits can be selected. When the MPX
interface is used, a bus width of 32 bits should be selected. For the synchronous DRAM interface,
a bus width of 32 bits should be selected by the MCR register.
When using the PCMCIA interface, a bus width of 8 or 16 bits should be selected.
The addresses of area 7 (H'1C00 0000 to H'1FFF FFFF) are reserved and must not be used.
Rev. 2.00 Feb. 12, 2010 Page 254 of 1330
REJ09B0554-0200
Area 3: H'0C00 0000
Area 0: H'0000 0000
Area 1: H'0400 0000
Area 2: H'0800 0000
Area 4: H'1000 0000
Area 5: H'1400 0000
Area 6: H'1800 0000
MD3
0
1
0
1
Figure 10.3 Off-chip Memory Space Allocation
Bus Width
Reserved (Setting prohibited)
8 bits
16 bits
32 bits
SRAM/synchronous DRAM/
MPX
SRAM/burst ROM/MPX
SRAM/MPX/byte control SRAM
SRAM/synchronous DRAM/
MPX
SRAM/MPX/byte control SRAM
SRAM/burst ROM/PCMCIA/MPX
SRAM/burst ROM/PCMCIA/MPX
The PCMCIA interface is
for memory and I/O card use