HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1118

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.3.1
SDIR is a 16-bit register that is read only for the CPU. Set a command via the serial input (TDI).
SDIR is initialized when TRST is driven low or the TAP controller enters the Test-Logic-Reset
state. The H-UDI can write to SDIR irrespective of the CPU mode. Operation is not guaranteed
when a reserved command is set to this register.
Initial value:
28.3.2
SDDR is a 32-bit register that comprises two 16-bit registers: SDDRH and SDDRL. SDDRH and
SDDRL can be read from/written to by the CPU. The register value is not initialized by the CPU
reset but is initialized by TRST.
• SDDRH
Initial value:
• SDDRL
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1034 of 1330
REJ09B0554-0200
Bit
15 to 8 TI7 to TI0 All 1
7 to 0
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit Name Initial Value
—
Instruction Register (SDIR)
Data Register H and L (SDDRH, SDDRL)
R/W
R/W
TI7
15
15
15
R
1
-
-
R/W
R/W
TI6
14
14
14
R
-
-
1
All 1
R/W
R/W
TI5
13
13
13
R
1
-
-
TI4
R/W
R/W
12
12
12
R
1
-
-
R/W
R/W
TI3
11
11
11
R
1
-
-
R/W
R
R
R/W
R/W
TI2
10
10
10
R
1
-
-
R/W
R/W
TI1
Description
Test Instruction Bit
0110xxxx: H-UDI, reset, negate
0111xxxx: H-UDI, reset, assert
101xxxxx: H-UDI interrupt
11111111: Initial value
Other than above: Setting prohibited
Reserved
These bits are always read as 1. The write value
should always be 1.
R
9
1
9
-
9
-
R/W
R/W
TI0
R
8
1
8
8
-
-
R/W
R/W
7
1
R
7
7
-
-
-
R/W
R/W
-
-
-
R
6
1
6
6
R/W
R/W
5
1
R
5
5
-
-
-
R/W
R/W
4
1
R
4
4
-
-
-
R/W
R/W
3
1
R
3
3
-
-
-
R/W
R/W
2
1
R
2
2
-
-
-
R/W
R/W
1
-
1
R
1
-
1
-
R/W
R/W
0
1
R
0
0
-
-
-