HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 412

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
(7) RAS Down Mode
The synchronous DRAM bank function is used to support high-speed accesses to the same row
address. When the RASD bit in MCR is 1, the read/write commands perform access using
commands without auto-precharge (READ, WRIT). In this case, precharging is not performed
when the access ends. When accessing the same row address in the same bank, it is possible to
issue the READ or WRIT command immediately without issuing an ACTV command in the same
way as in the DRAM RAS down state. Since the synchronous DRAM is internally divided into
two or four banks, one row address in each bank can be activated. If the next access is to a
different row address, a PRE command is first issued to precharge the relevant bank, and then
when precharging is completed, the access is performed by issuing an ACTV command followed
by a READ or WRIT command. If this is followed by an access to a different row address, the
access time will be longer because of the precharging performed after the access request is issued.
In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl +
Tpc cycles after issuance of the WRITA command. When RAS down mode is used, READ or
WRIT commands can be issued successively if the row address is the same. The number of cycles
can thus be reduced by Trwl + Tpc cycles for each write. Bits TPC2 to TPC0 in MCR are used to
determine the number of cycles between issuance of the PRE command and the ACTV command.
There is a limit on the time t
that each bank can be kept in the active state. If execution of a
RAS
program cannot guarantee that this time value can be observed so that an access to a different row
address occurs by a cache miss, auto-refresh must be set and a refresh cycle must be used that is
no more than the maximum value of t
. This makes it possible to observe the restrictions on the
RAS
maximum active state time for each bank. If auto-refresh is not used, measures must be taken in
the program to ensure that the banks do not remain active for longer than the prescribed time.
A burst read cycle without auto-precharge is shown in figure 10.20, a burst read cycle for the same
row address in figure 10.21, and a burst read cycle for different row addresses in figure 10.22.
Similarly, a burst write cycle without auto-precharge is shown in figure 10.23, a burst write cycle
for the same row address in figure 10.24, and a burst write cycle for different row addresses in
figure 10.25.
When synchronous DRAM is read, there is a 2-cycle latency for the DQMn signal that specifies
the bytes. As a result, when the READ command is issued in figure 10.20, if the Tc cycle is
executed immediately, the DQMn signal is not specified for the cycle Td1 data output. Therefore,
the CAS latency should not be set to 1.
When RAS down mode is set, and if only accesses to the respective banks in area 3 are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 10.20 or 10.23, and repeats the cycle in figure 10.21 or 10.24. An access to a
different area during this time has no effect. If there is an access to a different row address in the
Rev. 2.00 Feb. 12, 2010 Page 328 of 1330
REJ09B0554-0200