HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 708

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface with FIFO (SCIF)
The number of receive data bytes in SCFRDR can be found from SCRFDR.
(3) Break Detection and Processing
If a framing error (FER) is detected, break signals can also be detected by reading the SCIF_RXD
pin value directly. In the break state the input from the SCIF_RXD pin consists of all 0s, so the
FER flag is set and the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive
operation continues.
(4) Sending a Break Signal
The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and
SPB2DT in SCSPTR. This feature can be used to send a break signal.
After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the
SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark
state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high
level) in the beginning.
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized, regardless of the current transmission state, and 0 is output from the
SCIF_TXD pin.
(5) Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse.
The timing is shown in figure 17.22.
Rev. 2.00 Feb. 12, 2010 Page 624 of 1330
REJ09B0554-0200