HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1226

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Operand Access Cycle Break Condition Settings
1. Register settings: BASRA = H'80 / BARA = H'0012 3456 / BAMRA = H'00 /
On channel A, a user break interrupt is generated in the event of a longword read at address
H'0012 3454, a word read at address H'0012 3456, or a byte read at address H'0012 3456, with
ASID = H'80.
On channel B, a user break interrupt is generated when H'A512 is written by word access to any
address from H'000A B000 to H'000A BFFE with ASID = H'70.
Rev. 2.00 Feb. 12, 2010 Page 1142 of 1330
REJ09B0554-0200
A user break interrupt is not generated on channel A since the instruction access is not a write
cycle.
A user break interrupt is not generated on channel B since instruction access is performed on
an even address.
BBRA = H'0024 / BASRB = H'70/ BARB = H'000A BCDE / BAMRB = H'02 /
BBRB = H'002A / BDRB = H'0000 A512 / BDMRB = H'0000 0000 / BRCR = H'0080
⎯ Conditions set: Independent channel A/channel B mode
• Channel A: ASID: H'80 / address: H'0012 3456 / address mask: H'00
• Channel B: ASID: H'70 / address: H'000A BCDE / address mask: H'02
Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not
included in conditions)
Bus cycle: operand access, read (operand size not included in conditions)
Data: H'0000 A512 / data mask: H'0000 0000
Bus cycle: operand access, write, word
Data break enabled