HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 57

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.4 Operation.......................................................................................................................... 1092
30.5 Clock and LCD Data Signal Examples ............................................................................ 1106
30.6 Usage Notes ..................................................................................................................... 1117
Section 31 User Break Controller (UBC) ....................................................... 1119
31.1 Features ............................................................................................................................ 1119
31.2 Register Descriptions ....................................................................................................... 1121
31.3 Operation.......................................................................................................................... 1132
31.4 Usage Notes ..................................................................................................................... 1138
31.5 User Break Debug Support Function ............................................................................... 1139
31.6 Examples of Use .............................................................................................................. 1141
30.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1085
30.3.17 LCDC Power Management Mode Register (LDPMMR).................................... 1087
30.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1089
30.3.19 LCDC Control Register (LDCNTR) ................................................................... 1090
30.4.1 Size of LCD Modules Which Can Be Displayed with this LCDC...................... 1092
30.4.2 Limits on the Resolution of Rotated Displays .................................................... 1093
30.4.3 Color Palette Specification.................................................................................. 1093
30.4.4 Data Format ........................................................................................................ 1095
30.4.5 Setting the Display Resolution............................................................................ 1098
30.4.6 Power Supply Control Sequence Processing ...................................................... 1098
30.4.7 Operation for Hardware Rotation........................................................................ 1103
30.6.1 LCD Module Sizes that can be displayed with SH7760 LCDC.......................... 1117
30.6.2 Hardware Rotation Function............................................................................... 1117
30.6.3 Power Cutoff....................................................................................................... 1117
31.2.1 Break Address Register A, B (BARA, BARB)................................................... 1123
31.2.2 Break ASID Register A, B (BASRA, BASRB) .................................................. 1124
31.2.3 Break Address Mask Register A (BAMRA)....................................................... 1125
31.2.4 Break Address Mask Register B (BAMRB) ....................................................... 1126
31.2.5 Break Bus Cycle Register A (BBRA) ................................................................. 1127
31.2.6 Break Bus Cycle Register B (BBRB) ................................................................. 1128
31.2.7 Break Data Register B (BDRB) .......................................................................... 1129
31.2.8 Break Data Mask Register B (BDMRB)............................................................. 1129
31.2.9 Break Control Register (BRCR) ......................................................................... 1130
31.3.1 Explanation of Terms Relating to Access ........................................................... 1132
31.3.2 Explanation of Terms Instruction Intervals......................................................... 1133
31.3.3 User Break Operation Sequence ......................................................................... 1133
31.3.4 Instruction Access Cycle Break .......................................................................... 1134
31.3.5 Operand Access Cycle Break.............................................................................. 1135
31.3.6 Condition Match Flag Setting ............................................................................. 1136
31.3.7 Program Counter (PC) Value Saved ................................................................... 1136
31.3.8 Contiguous A and B Settings for Sequential Conditions .................................... 1137
Rev. 2.00 Feb. 12, 2010 Page lv of lxxxii
REJ09B0554-0200