HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 550

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Transfer Condition
Transfer source: external memory
Transfer destination: external device with DACK
Number of transfers: 32
Transfer source address: decremented
Transfer destination address: (setting invalid)
Transfer request source: external pin (DREQ1)
edge detection
Bus mode: burst
Transfer unit: word
Request reception priority: round robin
No interrupt request at end of transfer
DMABRG mode
Channel priority order: 2 > 0 > 1 > 3 > 4 > 5 > 6 > 7
(2) DMABRG Mode
Examples of data transfer from external memory to an external device with DACK using DMAC
channel 1 in DMABRG mode are considered here.
Table 11.11 (2) shows the transfer conditions and the corresponding register settings.
Table 11.11 (2) Conditions for Transfer between External Memory and External Device
Notes: 1. When DREQ0 to DREQ3 are specified as DMA transfer request sources in DMABRG
Rev. 2.00 Feb. 12, 2010 Page 466 of 1330
REJ09B0554-0200
2. Always write 1 to the CHSET bit when modifying the CHCRn value in DMABRG mode.
3. Always write 1 to the CHnWEN bit of the corresponding channel when modifying the
mode, any channels can accept the requests (a limitation on the use of channels in
DMABRG mode is only for a DMABRG request).
DMARSRA or DMARSRB value.
with DACK, and Corresponding Register Settings
Register
SAR1
DAR1
DMATCR1
CHCR1
DMARCR
DMARSRA
DMAOR
Setting
H'0C00 0000
(Accessed by DACK)
H'0000 0020
H'0000 22A5*
(H'0000 22AD*
H'0003 0040
H'0011 0000
(H'0091 0000*
H'0000 C201
1
3
2
when writing)
when writing)